Development Of 16-Bit Digital Signal Processor IP Core

With the development of communication technologies, utilizing digital signal instead of analog signal for storage and transmission is becoming more and more preponderant. Consequently, digital signal processing finds extensive applications. General purpose micro-processor is unsuited for the task of digital signal processing for the following reasons: The tremendous amount of data transferring in signal processing algorithm makes the bandwidth of the memory system of general purpose micro-processor becoming a bottleneck; a lot of repeat operation and special data addressing increases the load of system; multiplication is a very time-consuming task for general purpose micro-processor. For the very same reasons, DSP processor designed specifically for executing digital signal processing tasks is developed. These DSP processors use hardware directly implementing some function that is implemented by software in general purpose micro-processor. This hardware-intensive structure plus some special instruction designed specifically for signal processing makes it can quickly fulfill digital signal processing algorithms.TI's TMS320C5x DSP is a low complexity, high performance 16-bit DSP processor series with single instruction execution, four stage pipeline structure. The main task of this thesis is to design and verify a DSP core called HM320C50 which is compatible with TMS320C5x after being familiar with its architecture. And then complete the IP core standardization according to the approbated draft standard of China's IP Core Standard Work Group.Firstly, we introduce some structure characteristics of DSP processor which are suitable for digital signal processing. And then we describe architecture of HM320C50 from the aspects of instruction set, addressing mode, pipeline structure and memory system. Then, we divide the HM320C50 core into four parts of program controller, data space address generator, memory controller and operating unit, and complete the design implementation of each module. Lastly, after connecting the core with the existing peripheral module and constructing the verification platform, we carry out function verification of the DSP processor, including basic function simulation, high-code-coverage verification and gate-level simulation. Besides, we implement a method of combining formal verification and static timing analysis together, which is used as a quick and accurate alternative solution for gate-level simulation.