Research On Pipeline Architecture And Verification For Digital Signal Processor

With the process shrinking, the market rate of 32-bit fixed-pointed Digital Signal Processor (DSP) is rising. However, according to the statistics, 16-bit fixed-pointed DSP is occupying more than 80% market rate. By virtue of lower cost and power, 16-bit fixed-pointed DSP will keep playing an important role in applications. Contributing to the support of the High Technology Project of Zhejiang Province, P.R.China, a 16-bit fixed-pointed DSP, named MediaDSP1601, was developed successfully. As parts of research work, this paper mainly concerns DSP's pipeline architecture design, various hazards detection and elimination of pipelined DSP with heavily compressed instruction set, and comprehensive functional verification platform development.In order to speed up development, DSP design based on IP core is an effective solution, although such solustion brings out control problemses. In this paper, Distributed micro-control With Center macro-arbitration (DWC) strategy is presented, so that make the adjustment of pipeline architecture faster and easier. Take pipeline extension of Multiply-and-Accumulator as an example, base-core module and pipeline control unit module are modified by 0.90% and 4.31 % respectively. Furthermore, DWC strategy effectually balances control delay from pipeline control unit to pipeline stages. As a result, the variance of control delay is only 0.1145.The pipeline architecture of DSP cannot avoid leading hazards, which greatly prevent DSP with achieving ideal CPI performance. The adoption of heavily compressed instruction set makes data hazards dection much harder. A class-based data hazard detection method is presented to take advantages of the feature that the instruction fulfilling different functions applies special registers respectively, therefore it is more reasonable and simpler for the DSP with heavily compressed instruction set to check out data hazards than conventional methods do. With the assistant of hierarchical decoder and bypass circuits, this class-based detection method works well in the general applications of DSP. Furthermore, the results of synthesis illustrate that the implementation of this class-based detection improves the speed by 18.89%.As the complexity and quality expectation of pipelined DSP increased, while the time-to-market decreased, functional verification became a more difficult process and emerged as the bottleneck of the development cycle. In order to improve the efficiency and the effectiveness of functional verification, a comprehensive verification platform for pipelined DSP is presented, which is composed of automatic and completed instruction set verification sub-platform, high code coverage verification sub-platform, formal verification sub-platform, hardware based on FPGA simulation and verification sub-platform. The first sub-platform based on heuristic algorithm to verify the total instructions execution of the pipelined DSP, especially arithmetic function units, successfully achieves high statement hit rate close to 100%. While, the second sub-platform validates the complex pipeline mechanism of DSP completely and get 89% statement hit rate and 93% branch hit rate, which are 4.2-6.9 times more than usual application programs. The third sub-platform is used to check the consistency of netlists brought in each design phase. At last, the last sub-platform takes advantage of FPGA's phsical characteristics to simulate and verify the overall DSP, in order to decrease the risk of tape-out further.In a word, all of the above methods are successfully utilied in the development of MediaDSP1601 with exactly achieving all targets. Testing results illustrates that the correctness and efficiency of the pipeline architecture, the versatility of platform are both accomplished.