A Highly-configurable Verification System For Many-core Architecture

With the widespread use of new network applications such as social network, cloud computing and network multimedia, the scale of data to process get bigger and bigger. However, most current data centers use general-purpose processors, which do not take typical properties of high throughput application into account, including hard real-time, low latency tolerance and good scalability. As a result, it is necessary to design a high throughput processor with compatible network-on-chip. Due to the limitation of speed, accuracy and flexibility, state-of-art verification method and platform cannot meet the demand for high throughput many-core processor. This thesis proposes a flexible configurable FPGA verification platform. Multiple FPGA boards are connected by high-speed network for the research and verification of high throughput many-core processor architecture. Capability, network-on-chip and length of wire are all configurable in the verification platform.The main work of this thesis includes:(1) On the premise of feasibility, reliability and stability, the proposed verification platform achieves good flexibility. The hardware circuit of the whole configurable verification platform is designed and implemented.(2) High-speed DDR controller and PCI Express controller are designed and implemented based on Xilinx 7 series FPGA IP core.(3) Module-level verification of high throughput many-core processor is implemented on proposed verification platform.(4) System-level verification of high throughput many-core processor is implemented and applications can be run on the system.The design and the implementation of the configurable many-core architecture verification system in this thesis has been applied in National Major Project. The proposed verification platform provides reliable support for the research of high throughput processor.