Research And Design Of Low Power Multi-Core Digital Signal Processor

The Digital Signal Processor (DSP) usually needs to process the data with various precisions. The DSP with low-width need to split the high-precision operations into many low-precision operations, and this causes low speed. Though the DSP with high-width can process it fast, it becomes low performance when processing low-precision operations.This paper proposes a reconfigurable multi-core DSP, according to the operation precision, the multi-core DSP can be configured into three modes: four cores executing independent, splicing every two cores together or splicing four cores together. It can keep high performance even in different operation precision. This design improve and implement one 16 bits DSP, one 128 bits vector ALU and one 64bit vector MAC. Improve the data path of the DSP, replacing the original 32 bits scalar ALU and the 16 bits scalar MAC with the vector ALU and the vector MAC. This design uses various low power technologies in structure level, register transfer level and gates level, and reduce the DSP power efficiently.This design builds a performance simulation and power analysis environment, finishes the back-end flow. Taking the eight 8×8 matrix multiplication as example verification the DSP architecture. Based on Nanosim simulation, it shows that the multi-core DSP can work low power.