HPI Design And System Level Verification Of FT-C55LP Signal Processor

FT-C55LP is 16-bit fix-point programmable digital signal processor with high performance and low power. It adopts an advanced super Harvard architecture (with one program memory bus, five data memory buses, and six address buses) and the technology of a deep pipeline with 12 levels. The CPU is designed with Multiply and Accumulate (MAC) and Arithmetic and Logic Unit (ALU). It supports parallel processing for 2 instructions and the inner part of chip integrates a huge capacity of memory and numerous peripherals and it is especially applied in those portable products.Fortunately, I, as a participant for DSP's research, undertake two parts of this research, namely: the design and verification of FT-C55LP host-port interface; the design for system level verification based on this host interface and the system level verification.First of all, this paper has made an analysis and research on the system architecture, instruction system, pipeline, data stream element, address generation unit and program control unit, laying a foundation for the design of system level verification platform based on host interface and effective system level verification.This paper has made a study on the characteristics of the host interface of the current international major manufacturers' DSP products and its host interface-EHPI has been designed and accomplished according to the demand of FT-C55LP. This interface is a 16-bit enhanced host interface. The external host can directly access the RAM in FT-C55LP through it. In order to connect with different hosts, EHPI provides multiplexing mode and non-multiplexed mode to transfer data and address. The multiplexing mode provides a bus transport address and data while the non-multiplexed mode provides the divided addresses and data bus. This paper has provided the detailed design of this host interface and overall logic verification.As for the high-performance microprocessor design, verification is a highly challenging task, especially for the system-level verification. To develop an effective and easy-to-use system-level verification platform will play a critical role in the success of system-level verification. The author has designed a verification and test platform based on EHPI for FT-C55LP system-level verification. This platform consists of a kernel and some auxiliary tools. This kernel includes EHPI interface protocol model, initialization model, memory model and interrupt model etc.. The auxiliary tools include format conversion tools and automatic comparison programs for result. By using this verification platform, the users can conveniently run the test vectors and make a correct judgment for the simulation results.We has utilized this platform to have a system level verification for FT-C55LP, including initialization testing, instruction system testing and present vector testing etc. The design will be up to its function demands through the analysis on the verification results, design modification and re-verification and repeated iteration.