Research And Design Of 16-bit High Performance Embedded DSP

As the technology of microelectronics is advancing rapidly, the process technologies with the feature sizes of 0.18um and even 0.13um are widely used in commercial applications. With the development of microelectronics technology, microprocessors including digital signal processor (DSP) which represents the development level of integrated circuits are updated constantly and the processing ability becomes stronger and stronger. Up to now, 16-bit fixed-point DSP with the frequency of 600MHz can deal with 4800 million multiplier and accumulation computation (MAC) on only one second. Especially, the strong requirement for the third generation (3G) mobile communication applications promotes the rapid development of DSP. In near future, the applications based on Software Defined Radio (SDR) technology will need more powerful DSPs.Aiming to meet with the great demands for high performance DSPs, a DSP research project supported by national "863 projects" are being carried out in the Institute of Microelectronics, Chinese Academy of Sciences (IMECAS). As a part of this project, we designed a prototype DSP which is a 16-bit fixed-point DSP. This thesis mainly discusses the design of this DSP.In our DSP design, a four-level pipeline is used when designing the architecture, which predigests the control of pipeline without the loss of performance. The bus architecture modifies the Harvard architecture to provide enough data rate for computing units. The instruction set of DSP in mainstream is used which makes it more convenient for later development based on our DSP. The MAC unit of the DSP is fast enough to accomplish a multiplication and an accumulation in a single cycle. The parallel technology is used so that the DSP can do a computation and get two operands from on-chip memory in a single cycle. Zero-overhead loop is implemented and delay branch is realized to make the pipeline more efficient. Behavioral models are made for data path and control path. We obey the rules of Reuse Methodology Manual when designing on Register-transfer-level to make the codes re-usable. Function verification is done in hierarchy: On module level white-box verification is used and on chip level both white-box and grey-box. To improve coverage rate both random and specific stimulus are created. The area of the whole design is about 800Kgates and the time is 9ns.