The ASIC Design Of Chroma Resampling Algorithm

With the development of digital media technology, the sample formats of video signal have become more and more various. To share programs with different sample format as well as the video quality enhancement, the video format converter has become a crucial component in modern digital video equipments. This paper mainly describes the front-end ASIC design of chroma resampler's algorithm.Because of the different application in the digital vedeo broadcasting system, YCbCr sampling rates are different according to requirements. ITU (International Telecommunication Union Radio Communication Sector), have made all kinds of video standards such as 4:4:4, 4:2:2 and 4:2:0. 4:4:4 format is often used in the equipments of high quality requirements for signal processing. And the capture and transmission of the video signal format often use 4:2:2 format.Moreover, 4:2:0 format is also used in professional video equipments.Chroma resample is a very practical technology, which is closely related to the development and application needs. Many of the current format conversion chip market, which once applied only in the field of high-end technology, has been introduced into the consumer market. But so far, the chroma resample ship for high definition color video processing is few. The reason is that a tremendous amount of the algorithm system constitutes a bottleneck.The rationale and implementation method of the chroma resampler is introduced, and the Verilog HDL language is adopted in the systemic design. Its performances are analyzed and verified by simulation. In the process of chroma resampling module design, we focused on solving the luminance and chrominance signals output signal synchronization problem. To save on testing cost, the Design for Test was used in this module, and this is also one innovation in the subject. In addition, the paper also completed the whole system and sub-module function validation and adopted FPGA verification, which has laid a good foundation for the following ASIC synthesis, placement and routing.