Defog And Wide Dynamic Range Algorithm In Video Surveillance Implementation With ASIC

Recently, the Image Signal Processing (ISP) and computer vision algorithms have played critical roles in video surveillance security systems. While ISP deals with the preprocessing of the input video in surveillance system and computer vision algorithm focuses on intelligent analysis of surveillance system. Good ISP algorithms are of essential importance to post process on intelligent analysis of the HD video surveillance system. For instance, a video surveillance system operating in foggy environments or "The dynamic range of an image is not wide enough", one has to remove the fog and boost up the dynamic range of the image before compression and intelligent analysis. However, those ISP task are time consuming and occupies too much system resources. Actually, it is impossible to process HD video, in real time by using software method. Thus, in order to get rid of system performance and real time "sensing the real world", hardware implementation is needed to accomplish the ISP algorithms.In this thesis, the ISP two algorithms and its hardware realization are studied in detail. It not only can boost up the process speeds but can also improve the reliability of ISP algorithms in video surveillance system as well. The main works in this thesis are included as follows:(1) The dark color priori defogging algorithm is worked over in detail both on principle and implementation. The data structure of the algorithm is also designed to be versatile and adaptible for the other functionality of the ISP. The hardware description language (Verlong) is used to code for the algorithms.(2) Customizied the top mudule, stytem clock and memery distribution of the ISP, the streaming video input module, streaming video preprocessing module, defogging module and wide dynamic range module are defined as feature mudules. The input-output interface for those modules are also defined by using state machin.(3) According to the algorithm module resource assigned and SMIC.13um library, the constraints and optimized netlist file can be determined through logic synthesis from ASIC front end design. (4) After completing the front end design, the performance of static timing is checked to ensure stability and dynamic of the function. Finally, the anti-marker netlist is simulated to ensure proper functionality in preparation for tapeout.As the conclusion, The algorithms have been designed and mass produced in the SMIC130-nm process. The chip achieve the desired design goals of defogging and dynamic rang algorithms. The real implenment system shows that the ISP modules can dispose ISP of video format in realtime.