Implementation Of Baseline JPEG Coder Main Logic Circuit With Verilog_HDL

With the faster development of microelectronic technology, digital image encoding integrated circuit design have extensive application in many fields, image codec chip have become one of the competive area. Static image compression standard (JPEG) has the most effective compression technology with discrete cosine transform (DCT), by the Internal,as while the standard was also considered the best picture compression rule. In this paper,implicate IC logic design of JPEG encoder with VerilogHDL,including 2D-DCT, quantization and entropy encoding and data package module.This dissertation work on the IC skills and the basis knowledge of JPEG image processing and encoding standard, have the least number of multiplication unit in DCT algorithm,and Top-Down design process,pipeline structure, which the multiplier design tailored for DCT, Parallel input and reverse RAM structure, Z scan( Zig-Zag) for achieving better compression results, making the exchange coefficient reordering; Finally build Huffman entropy encoder and a concise data package(packer)module, also optimize the whole stucture, it shows this design improve processing speed and cut the cost; mean while,get the simulate results and synthesize graphics(RTL or gate-level maps) using Modelsim and Synplify pro,and the main JPEG encoder goes performancly.The main logic circuit of JPEG can be used in other system, and used in digital cameras,camcorders and Security, consumer electronic products and other equipments.