Dynamic Extended Compatibilities Scan Tree

Full-scan test is one of the most effective and popular design for testability technologies. Full-scan test technology changes the sequential circuit testing problem into the combinational circuit test problems, reducing the complexity of test generation and meanwhile increasing the coverage of faults but with great increase of the application time, data volume and power consumption of the test. Test application time in Full-scan test technology depends on the length of the longest scan chain. Due to the introduction of parallel scan chain mode, compressed scan test structures reduces a large number of test application time, but how to bridge the gap between external scan ports and a large number of internal scan chains in parallel on the input side is a complicated issue which should be settled by taking other factors into account because of the strong constraints at the interface between external scan ports and internal scan chains. In this regard, the scan test architecture based on scan cell compatibility came into being, one is to diffuse test vectors between scan cells in different compatible sets, such as scan tree architecture; The other is to copy test vectors between scan cells in the same compatible set, such as DCScan architecture. This thesis makes a study on scan tree architecture and DCScan architecture.In terms of three problems in tree-proliferation scanning for scan tree architecture-redundant power, excessive output ports and easy producing alias in response to compact, this thesis proposes a dynamic scan tree architecture which has low additional hardware overhead. The above problems are solved by scan chain disable and dynamic reconfiguration of scan path. Moreover, multiple scan chain compactors are compatible. The results show the performance of the architecture. As for the ISCAS'89 benchmark circuits, the average test response data volume is reduced by 97.19%at most compared with the original extended compatibilities scan tree architecture and is decreased by 88.77%when the test power on average is in 69.6%reduction.In terms of problems caused by synchronously outputting test response in the scan test architecture based on scan cell compatibility, this thesis proposes time-division-activated scan-output method. In the extended compatibilities scan tree architecture, this method can reduce a large number of test power while maintaining a minimum output; In DCScan architecture, this method greatly reduces the number of output ports and reduces peak power when scan shifting.