Logic synthesis for low power VLSI designs

Recent advances in technology and changing trends in consumer electronics have resulted in an increasing interest in low power digital circuits. The new interest in power efficient systems has initiated research for low power design at all levels of the design abstraction. This thesis explores the problem of power optimization during logic synthesis and provides the methodology and procedures necessary to perform logic synthesis on a Boolean network such that power is minimized after technology mapping.; During logic synthesis, power tracks well with the circuit area. This means that low area circuits also represent good low power solutions. In the absence of good models to estimate the power contribution of nodes in the technology independent circuit to the power of final circuit, low area solutions seem to also provide the best low power solutions. The first part of this thesis provides technology independent power models and shows that these models provide good estimates of the contribution of nodes in the technology independent circuit to the power consumption of the technology mapped circuit. Therefore making a strong case for technology independent power optimization.; This thesis also presents a complete set of power optimization techniques for logic synthesis and optimization. Power optimization techniques are presented which address the challenges faced in technology independent versus technology dependent phases of logic synthesis, multi-level versus two-level logic implementations and CMOS versus pseudo-NMOS versus dynamic CMOS logic styles.; The last part of this thesis describes the necessary components of a power optimization environment and presents a novel methodology for effective combination of the power optimization techniques developed in this work. These techniques, as well as the necessary environment for specifying, maintaining and also estimating power values have been implemented within POSE, the Power Optimization and Synthesis Environment. Results generated using the POSE system are used to demonstrate the effectiveness of the methodology presented in this thesis.