Research On Reconfigurable-based Network Packet Processing And Fast Development Approach

With the rapid development of modern Internet technology,various network appli-cations have penetrated deeply into every aspect of societyhave been seen in all walks of life:starting from the basic work needs,extending to people's clothing,food,hous-ing,transportation,social,and entertainment.The rich Internet applications are enriching people's lives,while but at the same time it posesbrings challenges to the existing basic communication network.These challenges are the following.Firstly,the continuous expansion of the net-work scale,the increasing number of network users year by year,and the mass transmis-sion of communication data,make ever-increasing Internet bandwidth stretched.At the same time,continuous changes in network properties are a challenge to the management capability of the Internet Service Providers(ISPs),as well as to network security.Sec-ondly,with the development of emerging technologies,such as cloud computing and big data technology,various new network platforms and applications,such as data centers,e-commerce,and video on demand continue to emerge which makes closed and rigid ex-isting network structures unable to provide sufficient support to these new application.In addition,the existing network structure is limited by the existing hardware technology,and the upgrading of the network equipment cannot be achieved without a replacement,which costs huge time and expense.Finally,the existing network development model of"manufacturer design and manufacture equipment+use by ISPs" makes various equip-ment standards in their own way.ISPs have difficulty in application,and do not have the right to speak;Network service providers cannot control the network applications rea-sonably and effectively,resulting in unsatisfactory service quality.Based on the above reasons,network technology researchers began to seek innovations in network process-ing technology,including changes in hardware platforms,architectures,and development technologies of network processors,in order to meet the demands of high performance,high flexibility,and rapid development.With the release of the high-performance open-source instruction set,the proposing of the new programmable architecture for network packet processing,the continuous de-velopment of the technology of reconfigurable Field Programmable Gate Array(FPGA),as well as the development of the Domain Specific Languages(DSLs),these technolo-gies which provide the possibility to meet the above challenges.This article first delves intoanalyze the characteristics of the traditional network processor architecture and the programmable "Match-action" architecture,as well as some of the key technologies in the process of applying the above two architectures to reconfigurable chips.Then,for the application of "Match-action" architecture,a development method of network packet processing based on P4 language and the reconfigurable chip is proposed.The specific proposed work is divided into the following three parts:First of all,for the low running frequency of the reconfigurable chip but the outstand-ing parallel processing capability,the network packet processing performance is improved by using a parallel structure,such as the multi-core infrastructure in the traditional net-work processors.But applingapplying it in the reconfigurable chips,each core will be limited by the on-chip storage space.As the number of cores continues to increase,the allocated storage resources of each core on the chip become more tense,and the problem of memory access conflicts is also more protruding.In response to address this problem,we useing a method to costomize a compressed instruction set which can reduce the num-ber of memory accesses and obtain a higher instruction cache hit rate,thereby improving the processing performance.Based on the open source instruction set RISC-V,this pa-per perform this method in detail.Experimental results show that the new instruction set customized by this method has higher compression efficiency and better processing performance than the original compression instruction set.Secondly,in view of the shortcomings of the implementation of the "Match-action"structure on the reconfigurable chip,a pipeline-based parser and deparser structure and its design method is proposed.Starting from improving processing performance and re-ducing processing latency,the structure of the "Match-action" engine is optimized and its pipeline is scheduled based on the dependency relationship.The specific work is as follows:·The pipeline-based parser and deparser are composed of multi-stage,and each pro-tocol in the packet header is parsed or deparsed step by step during the pipeline transmission process until all protocol are completely processed.The design method mainly analyzes the analytical relationship between the protocols in the pengding supported packet instanses,and draws it into a directed acyclic graph(DAG),which is used as the basis for the design of the pipeline.This design method solves the conflict and stall problems that may exist during the parsing or deparsing.·Aiming at the table structure in the "Match-Action" architecture,a pipeline sched-ule method is proposed.This method is mainly to establish a table entry dependency graph(TDG)according to the dependency relationship among the tables,and opti-mize it by using static scheduling.By using this method,it is possible to achieve higher parallelism and reduce the latency of message processing.In addition,the execution mode of the "Action" part of the table is changed,so as to completely get rid of the inefficient execution mode of implementing various logical operations by instructions.In addition,an on-demand design method is used during the hardware design,the bandwidth of the internal bus and the size of the tables are defined according to the de-sign requirements,so as to reduce unnecessary resource occupation.Experimental results show that the network packet pipeline structure generated based on this design method has the advantages of less resource consumption,high frequency,high throughput and low la-tency.The parser designed in this paper is in comparison compares with the state of the arts,and the throughput can reach more than twice on average under the same resource usage rate.Finally,a framework is proposed for quickly implementing the above "Match-action"pipeline structure to a reconfigurable chip.It first abstracts each functional module in the pipeline structure into different general templates,put them into a template library,and realize them by using VHDL.Then,it maps the network packet processing function which is described by the P4 program to the corresponding templates and instantiates them.Fi-nally it connects all the instantiated instances according to the design requirements and generates the synthesizable VHDL code to complete,so as to deploy the packet process-ing application.In addition,the concept of the Evaluation Library is proposed in this framework and applied to the optimization and performance estimation.Applying this framework enables network developers to focus on the development of network appli-cations without considering hardware details,thereby improving efficiency and reducing the difficulty in the development process.