Research And Design On An Improved General Reconfigurable Coprocessor For Multimedia Application

Reconfigurable computing is a general hardware accelerator. The system resources and implementation are determined by the structure of each reconfigurable cell. Meanwhile, the interconnection network has great influenced on the communication efficiency and configuration complexity.This work combines multiple reconfigurable cells into an 8x8 array, arranges in a 2-Dimension mesh structure and implements on SIMD.Propose a high efficiency general reconfigurable coprocessor model based on the MorphoSys model, improves the structure of reconfigurable cell by adding a control line to realize different functions with same context word. Design a 16x16 multiplier support not only integer but also complex multiplication. And the context words which fit for image manipulation are defined according to the Improved General Reconfigurable Array model.Propose enhancements on interconnection network with three levels cross connection and horizontal crossing quadrant connection which decrease the interconnect resources but greatly improve communication efficiency. The new array will simplify the context word and reduce the computing time, especially to the FFT and DCT transform.Finally, mapping the general implementation of imagine processing on the improved model, the performance evaluation of these applications indicates improvements in comparison with other systems.