Research And Implementation Of A Reconfigurable Coprocessor For FFT And Viterbi Algorithm

Under the background of the Software Defined Radio(SDR), this paper focus on the reconfiguration feature of SDR. Concerning FFT algorithm and Viterbi algorithm, which are two of the most widely used algorithms in digital communication system; we find some structural similarities between them by analyzing the computation process of FFT and Viterbi algorithm. This paper present a new reconfigurable butterfly unit based on their similarities. With this reconfigurable butterfly unit, we propose a reconfigurable coprocessor for FFT and Viterbi algorithm. The main contributions of this paper include:1. In traditional digital communication system, FFT algorithm and Viterbi algorithm are implemented separately, which need more hardware resources and lack of flexibility. This paper implements FFT and Viterbi algorithm in one reconfigurable structure. This method needs less hardware resources and achieves more flexibilty, which meets the requirement of the reconfiguration of SDR.2. By analyzing the computing process of FFT and Viterbi algorithm, this paper finds some common point between them and implements a reconfigurable butterfly unit on the basis of that common point. This reconfigurable butterfly unit only consumes 2/3 hardware resources compared with discrete implementation of the FFT algorithm and Viterbi decoding algorithm.3. Based on the reconfigurable butterfly unit, this paper proposes a coprocessor for FFT and Viterbi acceleration. The processor can switch between FFT algorithm and Viterbi algorithm. The transform point of FFT algorithm range from 4 to 1024; while the rate, constraint length and coefficients of Viterbi algorithm are configurable in a certain range.