The Study Of New SOI MOSFET Structure And Reliability In Nanometer Scale

SOI (silicon on insulator) technology which received much interest from the1960s and had a great development in1980s, had been used in the part of the commercial areas in1990s. Compared with bulk silicon technology, SOI technology gives many advantages over bulk silicon CMOS processing. In particular higher integration densities, small parasitic capacitance, latch-up immunity, and anti-radiation features. Furthermore, superior anti-irradiation characteristics allow SOI technology to be first used in satellite, aerospace and space applications. Several characteristics for fully depleted SOI devices like higher current drive capability, steep sub-threshold slope, and a good proportion reduced capacity make SOI technology have greater advantages when used in high-speed, low-voltage and low-power circuit and have great potential in nano-scale integrated chips. The ITRS Roadmap reports that it would be four SOI devices of five non-traditional MOS devices in the future. In this dissertation, the physical model, new device structures, materials, and reliability features of the SOI MOSFET are researched systematically, and the author’s major contributions are outlined as follows:1. The development of SOI technology and its advantages and disadvantages are studied. Then the direction of the SOI technology advancing in the modern era is cleared. In this dissertation, the mainstream SOI material processes, including the main process flow are introduced and the advantages and disadvantages of each technology are analyzed firstly. The channel surface potential model, the short-channel threshold voltage model and sub-threshold slope model of fully depleted SOI MOSFET devices with the physical principles of microelectronics technology are established by solving the Poisson equation. The relationship of silicon film thickness and the threshold voltage, and the sub-threshold slope and the channel length is discussed. Then, reliable theoretical support for future study on new SOI MOSFET device is given.2. An appropriate analytical model of SOI MOSFET is established by incorporating a hetero-material dual-gate (HMG) in the device. The improvement of the SOI MOSFET devices with the new gate structure is analyzed theoretically. Then a new hetero-material dual-gate strain SOI MOSFET (HMG SSDOI) based on strained silicon technology is proposed. Results from model and ISE simulation shows that a step potential in the channel is established by the new HMG SSDOI structure, reducing of the influences of the voltage of the drain to the potential barrier of source, restraining the effects of drain-induced barrier lowering greatly and improving the off-state characteristic of the device. Furthermore, the initial speed of the carriers into the channel is increased and a faster saturation speed by step potential is obtained. Therefore, the carrier mobility is greatly increased by introducing the strained silicon technology and the SOI MOSFET device performances have been improved greatly.3. As the gradual decrease in device feature size, the impacts of the gate dielectric thinning have been noticed more. In this dissertation, the preparation of hafnium dioxide with atomic layer deposition (ALD) technology and the method of testing the performance of the hafnium dioxide film in experiments are described. A threshold voltage model for the novel high-k gate dielectric material SOI MOSFET is established to analyze the effects of quantization and high-k gate dielectric materials. In addition to the use of the new gate dielectric material, the gate dielectric structure is also being adjusted. The analysis results show that the leakage current at the gate of the device is reduced efficiently, and suppression capability of the DIBL effect is improved. Moreover, the initial speed of the carrier to enter the channel is greatly increased leading to improvement in the transmission performance.4. A new strain technology into SOI devices which modify basic Si material parameters by band structure Si material changes is introduced in this dissertation. Two mainstreams SOI devices strain structures (SGOI SSDOI) are studied focusing on SIMOX, bonding technology and "the Ge enrichment" technology. Then the channel surface potential model and threshold voltage model of SGOI are established. The analysis results indicate that the performance of the SOI devices is greatly improved, the DIBL effect and other secondary effects are further restrained. It is also worth to note that a good agreement of model results with ISE simulation structure fully demonstrates the validity of the proposed model.5. Serious self-heating effect in SOI device structure is an important field. In this dissertation, modification in both materials and structures are made to suppress the self-heating effect in SOI. In the proposed model, the traditional SiO2is replaced by A1N materials, voids are opened in the buried oxide layer, and the dual-stepped structure is used in the strained SOI device buried layer. The simulation results indicate that the thermal conductivity of the buried oxide layer is changed, reducing the self-heating phenomena. Meanwhile, the DIBL effect is greatly suppressed by the presence of voids. Furthermore, the temperature of the device is reduced by dual-stepped buried layer structure, restraining the self-heating effects. In order to optimize the device performance, several series of experiments of the buried layer structure are made. The simulation results of two new devices show that the self-heating effect is greatly restrained by the new structure and material in SOI devices and the performances are greatly improved.In summary, several novel SOI MOSFETs are proposed and studied on the device characteristics in this dissertation. Quantitative theoretical analyses are taken through numerical simulation and modeling methods to a great deal of basic mechanism problems. A lot of meaningful results are obtained and the guideline for the nanometer SOI MOSFET is presented in this dissertation.