Research On Fabrication And Characteristics Of Novel Nano-Scaled MOS Device

Gate-all-around Si nanowire MOSFET (GAA-SiNW) is considered to be the most promising device structure to scale down CMOS to the end of the technology roadmap due to its excellent short channel immunity and high drive current. Peking University has already proposed a GAA-SiNW fabrication method based on top-down approach.Firstly, we have systemically investigated the sacrificial oxidation process in this paper, based on which Si nanowires have been fabricated. The impacts of oxidation temperature, oxidation time, and initial size of silicon fins on the morphology of Si nanowires have been studied in detail. Moreover, we have successfully fabricated high quality Si nanowires with diameter about 5 nanometers. Secondly, GAA Si nanowire SONOS with an acceptable window about 2.5 volts have been successfully fabricated on silicon substrate by conventional CMOS process. However, a parasitic bottom memory will be inevitably formed. Therefore, we proposed a possible solution to suppress the negative impact of parasitic bottom memories.Finally, we have fabricated GAA-SiNWs on SOI substrate. The I_on/I_off of the NMOS and PMOS is 1×10⁷ and 1×10⁶, respectively. The subthreshold slopes of NMOS and PMOS are 75～80mV/dec and 65～70mV/dec, respectively, which reveal promising application prospects of the GAA-SiNW structure in integrated circuit.