Research On FPGA-CPU Debugging Technology Based On Nios Ⅱ

In this paper, the technology of FPGA-CPU debugging is discussed based on Nios II embedded processor. The characteristics of Nios II embedded processor is studied. The hardware and software design of the FPGA-CPU debugging system are accomplished. Two different types of FPGA-CPU are debugged with the debug system developed . The testing datum are analyzed.As for hardware design, in order to control and monitor FPGA-CPU, several circuits are designed, which are the dual-port memory circuit, control circuit and scanning circuit etc. Besides, all inferface circuits between debuging system and FPGA-CPU are achievedAs for software design, the debuging software based on Nios II processor is completed, which can operate the dual-port memory, loading and controling testing programms. The software can monitor the FPGA-CPU running state. All information inside the FPGA-CPU can be obtainded , including registers , data bus and address bus etc. Several debuging mode are accomplished. They are single clock debugging model, one-step instruction debugging model, and breakpoint debugging model. These modes can be used alone or alternately.In order to increase the efficiency of the debuging system, a compiler software has been completed, with which the assembler programmers can be compiled into their machine language.On the implementation of debugging system, two types of FPGA-CPU are tested, whose instruction system and architecture are widely different. The debuging result demonstrates that the technology of debugging based on IP reuse can debug FPGA-CPU efficiently. The debuging system and the FPGA-CPU can be in one chip, achieving the seamless linking between the these parts.