The Hardware Decoding System For LFM Signal Based On Nios II Soft Core Embedded Processor

This paper presents a SOPC(System On Programmable Chip)system based on IP(Intellectual Property) soft core technique and combine with EDA(Electronic Design Automatic) tools and DSP(Digital Signal Processing) technology in modern communication, which are realized on a single FPGA(Field Programmable Gate Array)chip This system is decoding receiver for communication system with LFM(Linear Frequency Modulation) as coding signal, using Nios II as the base-band processor and FPGA technology as FE(Front End) processing.SOPC system is not a single electric circuit element with homogeneous function any more, but a project that integrated complete system function module such as DAQ(Data Acquisition), data processing, IO(Input/Output) ,etc into a single or a few chip. SOPC system integrate the CPU(Central Processing Unit), memory, IO ports and the other system module into a FPGA chip to realize a embedded system with complex functions. Nios II embedded processor a general-purpose RISC processor core for SOPC system developed by Altera corporation and now progress to second edition. Nios II provide to designers with IP core and its programmable feature brings more flexibility and a new way of SOPC to embedded designers.The primary content studied in this paper is to realize a receiver on a single FPGA as a SOPC system with communicating terminal function such as signal acquisition for LFM, zero-IF(Intermediate Frequency) processing in DDC and multiple correlation, etc.The background in application area of LFM signal is introduced first and goes into the development history and state of arts about SOC(System On Chip) with several evolution technology of SOPC. Afterwards, the LFM coding and decoding technique and principle are examined in detail with property at system level, especially focus on the study of FPGA implementation of digital signal processing applied in modern communication, spread spectrum communication, soft radio, etc. At last the detail of system design and realization on a FPGA chip are presented.