Design And Realization Of Embedded Information Transmiting System Based On Nios II Soft CPU

The thesis follows on the heels of trend of embedded system designtechnology, Introduces a new technology of embedded system design-SOPCtechnology, and applying it to research of communications. Nios embedded processor is a 32/16-bit RISC processor soft core developed by Altera that facilitates SOPC design on FPGA.The thesis analyses the Nios II processor soft core, including structure of system , performance of working and characteristic of Avalon bus .the Nios II processor soft core is the latest technology of SOPC. Nios II is a 32-bit RISC processor soft core;Nios is a kind of CPU that designed for SOPC specially. For embedded system designer, it's a kind of IP core. Nios has the characteristic of reconfiguration, which brings more flexibility to the designer. Nios has offered a kind of brand-new train to Embedded System designer. It can accomplish the SOPC design based of FPGA. It realized a reconfiguring embedded system by embedded the Nios soft core and others application IP discreteness in FPGA.The thesis research and realize the application of communications. Apply Nios II soft core in the master board , As a coprocessor, partaking functions of the main CPU. using one piece of Stratix II FPGA chip to realize the function of the communications management of main board and sub board.At the end of the thesis, the system design is realized and validated successfully in this thesis by the result of testing, try the new SOPC technology.in development of software and hard design, It is used as a coprocessor of main CPU to realize the system level functions, alleviating the use of peripheral parts and accelerating the realization of application functions. It shortens the design period, saves upgrade cost and optimizes performance and resources.