Design Of Multi DSP Embedded System Based On The Technology Of Nios SOPC

Accompanying with the development of microelectronic technology and the improvement of field programmable gate array logic (FPGA, Field Programmable Gate Array) technology, on-chip programmable system SOPC (System On a Programmable Chip) technology is becoming a new aspect of embedded systems technology.In the field of real-time image processing, radar signal processing, software radio, electronic countermeasures and 3G simulation calculation, the embedded systems is requested with data-handling capacity, high data throughput and multi-tasking real-time processing functions. Therefore, the embedded systems which based on multiple DSPs are carried out, when the systems which based on single DSP are not satisfied with the requirement of real-time and high-speed computing.In this thesis, according to the QDMA character of DSP and the implementation of SOPC on the FPGA, an embedded system of multi DSPs was designed and achieved. The embedded platform has the following main features:In this thesis, according to the QDMA character of DSP and the implementation of SOPC on the FPGA, an embedded system of multi DSPs was designed and achieved. The embedded platform has the following main features:(1) Reconfigurable strong: designers can make reconstruction design and upgrade design on the hardware platform on the basis of FPGA reconfigurable characteristic and demand, without any hardware changes.(2) External high-speed communication interface: The system provides a 64-bit data width, 200 MHz clock interface and 12 control signals for external high-speed communication interface. This interface not only make the system with other systems for high-speed data transmission, but can also make two of the system docking, and make of a more powerful multi-DSP embedded systems.(3) A strong ability to deal with: the platform capacity of up to 64000 MIPS (million instructions per second ).In this thesis, an embedded system of multi DSPs was designed, achieved and verified as the hardware platform for B-ultrasound fetal sex shielding algorithm processing platform. The results of the experiments show clearly that the performance of this proposed embedded system which based on the technology of NIOS's SOPC is stable and superior, and owns the ability to be used in the field of radar signal processing, electronic countermeasures, high-end image processing, et al.The entire B-ultrasound fetal sex shielding system is composed of two parts: hardware and software. The objective of this thesis is creating the multi-DSP hardware platform.The hardware platform bases on the Nios SOPC technology and digital signal processor: TMS320C6416T. The thesis is mainly divided into four parts. Firstly, the SOPC technology, the Nios CPU's architecture and its bus structure are introduced. And also the SOPC EDA tools,hardware description language and the multi-processor design method which based on the Nios SOPC technology are briefly introduced. Secondly,the features,internal structure, external interface and other resources of the DSP TMS320C6416T processor are discussed. At last, the thesis briefs the hardware platform as the algorithm processing platform of B-ultrasound fetus sex shielding, and also gives the test results.