Research And Implementation Of Asynchronous Data Demultiplex System Based On FPGA

With the development of modern telecommunications, there is an increasing demand of transmission speed and bandwidth. In order to use transmission channel more effectively, Digital Multiplex Technique is widely used to multiplex and demultiplex different speed level digitals.Digital Multiplex Technique has been applied in many fields. Public communication network has formed E1 and T1 system, but most of the multiplex system devices base on ASIC chips, thus far FPGA is seldom used in appropriative chips. In digital Multiplex system, corresponding to multiplexer at the transmitter, demultiplexer at the receiver must demultiplex and distribute the multiplexed data with high efficiency and accuracy, and this is a key process to the whole system. This thesis researches an appropriative demultiplexer aiming at serial asynchronous data and its implementation on FPGA. This thesis first goes deep into asynchronous signal behaviors on FPGA platform, gives synchronizer for asynchronous clock domains and system clock design. The Knot Synchronizer this paper gives rise to can solve the problem while signals passing from a faster clock domain to a slower one. Then, modules of demultiplexer, including bit positoning, frame positioning, signaling processing and asynchronous FIFO are researched under the circumstance of cross-clock domain. The Full/Empty signs are triggered by a method of asynchronous compare, which to some extent would avoid "conservative" Full/Empty signs in normal asynchronous FIFOs.The system principle and key modules discussed in this thesis are cross-sectional, the methods provided coulde be references model to demultiplex serial asynchronous data in related applications.