Telemetry Module Automatic Testing System Of Digital Demultiplexer Design

Telemetry module automated test system is used to test the performance indicators oftelemetry module atomaticly and comprehensively, in order to enhance the rapiddevelopment level of the telemetry device. As the main part of telemetry moduleautomated test system, digital demultiplexer used to provide the data source for theautomatic test system. This paper first introduces the development of automatic testsystem and its composition and application of FPGA technology in electronictechnology now, then introduces the composition of automatic test system oftelemetry module, then expounds the principle of digital multiplexer, proposed thesoftware and hardware scheme of digital demultiplex system, the digitaldemultiplexing is divided into three modules PC machine, a lower machine andhardware circuit, respectively from the two aspects of soft, hardware details processdigital demultiplexing module design process and analysis of key issues. Finallyintroduces the digital demultiplexer appeared in system debugging of the situation andthe problems in the design of.In terms of hardware，using hardware description language based on FPGAdynamic reconfiguration, digital PLL clock extraction circuit, digital multiplexingprinciple frame synchronization circuit and the hardware controller based on SDRAMcontroller is designed. Taking into account the modern testing system parameters iscomplex and changeable situation; the designed circuit can be configured on theparameters by computer. This paper gives some code design and simulation results. Insoftware design, using SOPC technology, constructs the Nios soft-core processor inthe FPGA platform, and uses the Nios IDE comes with μCOS real-time operatingsystem and transplantation of TCP/IP protocol stack to achieve the communicationbetween upper monitor and lower machine.Final design project completed system hardware and software design, codingmodule can complete the dynamic calibration and accuracy of measurements.Practical application shows that the digital demultiplexer meet the requirements andtargets, bit synchronization module enables819.2K baud clock bit synchronizationtime in42microseconds or less, frame synchronization can achieve8-channel digital signals and64-channel analog signals data error less than1%, the cache module canachieve data100seconds of data storage, digital tap module can perform a variety ofencoding formats digital tap. Has a high degree of automation and reliableperformance.