Fpga Implementation Of Digital Multiplex

The subject is the terminal of a optical transmission system which belongs to a cooperative project with a company. The function can be accomplished that multiplexes three branches of 20Mbps into one data flow of 60. 8Mbps and demultiplexes the data flow into three branches, positive justification used during the course of multiplex. In the paper, common problems on positive justification are analysed, such as frame assignment, transition process, jitter. Then the frequency spectrum of a gappy clock is analysed which will be recovered by PLL. At last, synchronous design rules for FPGA are discussed and illustrated through several examples in the subject. The following task is performed by the auther: 1. Multiplex system, demultiplex system and frame assignment system are accomplished by FPGA. 2. The gappy clock is recovered by analog PLL. 3. The frequency spectrum of the gappy clock is drawn, which is conducive to the design for PLL. 4. The error rate is tested for the whole multiplex device. l0~ can be reached.