| The major challenge the IC design is confronted with has been to design with far more complex functionality and domain diversity. At the very top of the challenges to be solved is verification. In modern ASIC design, a single verification method or technique could not be used to solve the problem. Instead, a complex sequence of tools and techniques are needed to reduce the number of design errors to an acceptable minimum.In the 64-bit embedded CPU development, we use a variety of verification methods to ensure the CPU meets the functional requirements. FPGA (field programmable gate arrays) verification has been one of the most important supplement strategies.The paper describes the structure of the 64-bit CPU and makes the FPGA strategy on the FPGA we chose- XC4VLX60. Then the paper analysis and study the problem occur during the FPGA verification establishment process, mainly about the RTL partition and conversion, the implement on FPGA and the debug problem. Based on the former study, we establish the FPGA verification for the 64-bit CPU and develop kinds of useful debug methods to debug including ChipScope, UART and Perl.At last in conclusion and expectation, this paper concludes some knowledge that is useful for FPGA verification work. And it gives some proposal about future job by listing some fields that should be researched. |
