Research On The Verification Of Debug And Trace Based On UVM Methodology

The quality of the code implemented in the early stages of the digital chip project is primarily guaranteed by functional verification.Complete functional verification ensures that the functional description of the design document is consistent with the implementation code.Thus,the focus of functional verification is reflected in the early detection of code loopholes,saving project development costs.As a technology used in the functional verification process,UVM can efficiently implement completeness validation.This paper realizes the reusable verification environment through the design and analysis of the verification platform,which has advantages in improving the efficiency of verification and verification of completeness.Firstly,the characteristics of System Veriolog language in digital chip functional verification are analyzed by comparing with pure hardware description language and object-oriented programming language.System Veriolog selectively inherits both the hardware and software advantages of the language;and then analyzes the UVM base class library and the verification component based on the class library implementation,the component model can quickly complete the verification platform to build the work;UVM unique hierarchical platform architecture and The perfect operation mechanism makes the verification personnel released from the complex verification platform construction work,pay more attention to the realization of the verification function point.Next,the verification object debug module is described.By comparing the traditional JTAG chip debugging method,the verification object debugging module not only inherits JTAG's existing function,but also provides the real-time debugging ability of the system kernel module and the high-bandwidth system tracking capability for multiple data sources.The tracking module allows the test engineer to evaluate the quality of the chip after the chip is completed and find the root cause of the chip's defect.It is also easy for software engineers to use the module for software debugging,detection of internal module operation.The tracking debug system has some advantages over ARM's Coresight tracking and debugging architecture in terms of chip area,power consumption,and flexible design for specific modules.The verification function points are extracted again according to the priority order according to the authentication object.The method and level of authentication should be used to divide the function points into different points.Write the UVM authentication component,use the reuse idea to complete the platform component construction.The construction of test sequence library is completed by hierarchical modularization.Through the simulation and debugging of multiple iterations and results analysis,for the different verification phase using the corresponding verification strategy,and constantly improve the function and code coverage,and ultimately to verify the completeness.Finally,the verification methods and simulation results of each function point are analyzed.i Combined with the construction of the tracking module to verify the platform and code coverage and functional coverage of 100% of the index requirements,it is concluded that UVM random test have significant advantages than direct test in verifying efficiency,reusability and completeness.And put forward the platform in the reusability can continue to improve the part.