Implementation And Verification For A New SoC Low Power Debug System Strategy

As the integration level and complexity of System on Chip(SoC)increase,traditional presilicon verification method can no longer guarantee that the design is free of error.By a proper design of On Chip Debug System(OCDS),potential defects could be located and solved in a prompt manner.It has become necessary that the modern SoC works in a power saving mode most of the time to address the increasingly severe issues associated with power consumption.While a series of power saving technologies,e.g.turning the power off and lowering the clock frequency,are utilised to optimise the performance,these changes also introduce uncertainties to the circuit.Thus it is necessary to propose a new SoC debug system designed for power saving modes based on the OCDS structure to resolve the issues associated with debug information losses during reset when the SoC works in power saving modes.Firstly,this thesis begins with the post-silicon low power debugging requirement background,bring out a baseband chip designed by Intel corporation as an example,thoroughly analyzes a kind of multi-core OCDS architecture which mainly consist of Debug Access Port(DAP),ARM and ARC Debug Interface based on ARM Coresight technology.This debug system allows the debugger could initiate totally debug access in an extensive range covered all the SoC debug resources.And then discusses the specific impact of current low power mode technology to debugging,that made a good preparation for the latter design of the low power debug system.Secondly,in order to start debug access towards target processor in low power mode,this paper raise a wire connection rule for power up signal groups,and researches every processor's low power control method.Aims to the relationship and the difference of processor system control,designs disparate low power debugging system for them: brings up the power and reset override hardware design for the processor which could separate the power and the reset control of debug and function logic;uses debug save and restore software compensation strategy for the processor that couldn't divide the debug and the function logic away.By comprehensively using hardware and software project,finally achieved the overall support of the debug to SoC in low power mode.Depending on the most popular and also important oriented test method in verification,this paper premised a pre-silicon debug replace plan to do the dynamic simulation to the low power debugging system.Uses routine debug test to verify the correctness of OCDS;and then make use of the external JTAG interface and the assembly instruction to implement the software and the hardware execution setting,in the way of config comparing experiments to do the verification for the new SoC low power debug system strategy in different low power scenarios.The result convincingly shows that the legitimacy and the feasibility of this scheme.The final propose of SoC debug system is to service for post-silicon debugging,at the end of this paper,under the post-silicon debugging environment,the debugging typical lowpower scenario testcase is tested again on a real chip.Conclusion proves that the new SoC low power debug system strategy we raised before could not only let the system to keep the debug information in the low power mode,but also make the debug feature takes effect.This eventually resolved the technical issue which chip couldn't be debugged in the low power mode.