The Design Of Debug Platform Of Video SoC

This paper introduces a design of test platform which intends to be employed to debug VDEC IP in Video SoC. The advantage of the test platform is that it can eliminate the interference comes from backend processing and focus on the performance analysis of the decoder module, thus to achieve an ideal performance test results.Compared with traditional SoC performance test, the advantage of this design is it obtains excellent controllability and obversvability for a specified IP. The final data will be sent to external display and the protocol monitoring equipments.This paper emphasizes on the FPGA design and hardware debugging of the test platform in which FPGA implements SDI encoder as protocol layer requirement, while hardware design makes the SDI physical layer possible. The detailed principle of every module in the SDI encoder and the debugging interface module are also described in this paper.The platform has been widely adopted in several SoC projects which is proven to be a stable and efficient testing system.