NoC Based SoC Debug

With the ever advancement of the semiconductor technology, nowadays an entire system is able to be implemented on a single chip, known as system-on-a-chip (SoC). The development of SoC devices is based on the design reuse philosophy, i.e., they are created by combining tens or even hundreds of pre-designed IP cores (e.g., processors, DSPs and memories), infrastructure IPs and custom user-defined logic (UDL). The advantages in terms of the performance, cost and power consumption make SoC perfect for the mobile device, telecommunication and network equipments, digital TV and setup box, and various consumer products.As the complexity is the fundamental characteristic of the SoC, the bugs hiding in the design or implementation are unavoidable. Although huge efforts are paid during the design and verification, a bug-free first run is an impossible mission. When hardware or software errors are found, the debugging process is triggered to find out the root cause. To improve the debug quality, the effective and efficient debug technique is the key.Meanwhile, as the device feature size is continuously shrinking and the bandwidth and other QoS requirements are more stringent, traditional shared-bus architecture will no longer be able to meet these requirements of a complex SoC, especially multi-process SoC (MPSoC). Network-on-Chip (NoC) architectures have emerged as promising alternatives to address the problems associated with on-chip buses by employing a packet-based micro-network for inter-core communications and are generally regarded as the most promising on-chip communication solution for future giga-scale MPSoCs. However, existing SoC debug techniques mainly target bus-based systems originally and are not readily applicable to NoC-based SoCs where a totally different and more complex communication scheme is employed.Motivated by above observation, in this dissertation, we address key SoC debug requirements and present debug platforms, architectures and strategies for debugging NoC based SoCs. In the following chapters,â– we first give the background of current SoC debug techniques and discuss new challenges introduced in NoC based systems. Then, by identifying the problems and analyzing the related researches, we explain the motivations and show the main contributions of this work.â– After analysis of the characteristics of the NoC, we then present a novel debug platform for NoC based SoC to fulfill the debug requirements. It is build up by three main parts: on-chip debug architecture, including a debug agent (DA) and debug probes (DPs), off-chip debug controller (ODC) and supporting debug control software. We also build an experimental simulation platform on which the presented debug techniques can be verified. A comparison to current solutions shows the novelty and advantages of presented debug platform.â– As one of the focuses of this paper, the in-depth analysis and experimental design of the Debug Agent and Debug Probe are presented in detailed. The DA is the access point of the on-chip debug services and provides the debug and trace channels for accessing all on-chip debug resources. The DP is inserted between every CUD (Core Under Debug) and the NoC, which supports the concurrent debug and tracing of the core and inter-core transactions. The experimental designs of the DA and DP demonstrate their functionalities and the area efficiency.â– Based on the functions and features provided by the debug platform, we present a debug command scheduling algorithm which supports the multi-core debug synchronization; and two novel multi-core cross-triggering strategies: "multi-pass" debug strategy and "in-band" trigger event transmission mechanism, which well solved the cross-trigger problems for certain debug applications.â– Finally, we conclude the research works and present some interesting but not addressed research topics in this direction.