Based On The Dro And Sampling Phase-locked Technology 6.4ghz Low Phase Noise Oscillator Source

With the development of radar and wireless communications, the request for the local oscillator is higher and higher in the system . Seeking the oscillators with the lower phase noise, more highly pure spectrum and more highly stabilization has became the tend to develop. At present the prevalent frequency-divided PLL oscillators have obtained excellent performance. While Sampling PLL oscillators have not been paid attention yet, the applications about them are limited at few special field, for example, space exploration and measurement instrument. But it can't obliterate their advantage at phase noise performance. On this background, the task is to realize a 6.4GHz low phase noise sampling PLL oscillator.DRVCOs and DROs are applied abroad to frequency synthesizers and microwave oscillators because of their excellent phase performance, spectrum purity and stability. At present ,internal DRVCO and DRO productions mostly are achieved by experiences of engineers.It is difficult to breakthrough the performance and target in existence for lack of deeply analysis and instruction in theory. Altough Sampling PLL is not new technology , the means to realize oscillator in higher_frequency band by combining it with DRVCO was "lower_frequency Sampling PLL+frequency_multiplying".In fact the reason is the juvenility of narrow pulse formation technology to restrict the upper_limit operating frequency of the SPD. With the continual development of the pulse formation technology, the upper_limit operating frequency of the SPD becomes higher and higher,and can satisfy our request of higher operating frequency. So the author improves the aforementioned project ,i.e., the new one is to realize the oscillator in C band with directly sampling signal of 6.4GHz from DRVCO and without frequency_multiplying. The task has difficulties as following:Design and debug the DRVCO;Design the pulse formation circuit and periphery circuit of the SPD;Design and debug the PLL 。The paper analyses deeply the principles of DRVCO and all kinds of structures firstly. And then it introduces the principles of Sampling PLL oscillator. Next the paper expatiates the design, simulation and debugging of the DRVCO and PLL in the task At last, the testing results are analyzed and some solutions to the shortages put forward .