The Design Of 1GHz Clock Circuit With FPGA

The Daya Bay reactor neutrino experiment is a neutrino-oscillation experiment designed to measure the mixing angleθ13 using anti-neutrinos produced by the reactors of the Daya Bay Nuclear Power Plant.Comparing neutrino flux and energy spectrum of the near and far detector can get information that whether the neutrino-oscillation experiment occurred,and then ascertain the oscillation parameterθ13 . The optical signal from detector can be changed into electric signal by a transfer device, and amplifying the electric signal will calculate the information of energy and position about the particle, finally these information can be read out by high speed waveform acquisition circuit.The high speed waveform acquisition circuit has an external clock interface to ensure the sampling rate and amplitude resolution, all plug-in board synchronous working and pinpoint timing . Clock source is an important sub-circuit in high speed data conversion system,because timing precision will directly effect the dynamic performance of ADC. For the sake of minimizing the effect, the clock circuit should be designed with low jitter or low phase noise,else the system dynamic performance will not depend on front-end analog input or the performance of ADC.This article introduce the high speed circuit from device, hardware principle design, PCB design and circuit debugging, and put emphasis on realizing 1GHz clock hardware design and PCB design. The operating principle of circuit is that using FPGA for controlling the clock-synthesizer. Because it is a high frequency clock signal, the output use LVDS signal. Considering completeness and anti-interference of high frequency clock signal, the PCB designed into a four layers board.The debugging result proved that the circuit can realize 1GHz clock to output. Because the clock-synthesizer chip is programmable and it has the potential of generating the higher clock , the design can be further improved to obtain higher frequency clock signal.