The Design Of A Clock Generator Based On DLL

Phase locked loop (PLL) and the delay phase locked loop (DLL) are the most important part of the modern electronic equipment, and be widely used in the timing circuit and clock synthesizer circuit. Delay phase‐locked loop compared to phase lock loop, has characteristics of better stability, smaller clock jitter. As the development of the very large scale integrated circuit and the high‐speed signal processing, there has a increasing demand for a high performance on chip clock, this paper designs a clock synthesizer used the delay phase‐locked loop technique.This paper introduces the basic theory of PLL and DLL. Firstly, ac small signal analysis was did based on the traditional DLL, summarized the reasons of failure locking and harmonic locking, deterioration of the jitter performance problem during wide locking rang operation and put forward the solutions. Secondly, in the circuit level design, designed a start control phase detector, it can set the VCDL delay to the minimum value when the DLL starts to work, so as to avoid the false locking and harmonic lock problem. Designed a high performance charge pump with a coarse tuning circuit, which can reduce the locking time; used the differential input/output voltage‐controlled delay unit, optimized the clock jitter characteristic. Designed a high speed clock synthesizer using the DLL multi‐phase output of the VCDL, and added a duty ratio control circuit after the clock synthesizer, which is used to regulate the high frequency clock duty ratio. Finally, did the Monte Carlo simulation and corner simulation on the whole circuit to verify the rationality of the design.This design uses a0.18um CMOS (Complementary Metal Oxide Semiconductor) process, the layout was implemented by Cadence virtuoso layout XL tools after the simulation of the whole circuit. In the process of layout, confirmed the reasonable layout of every modular and finished the submodule’s layout. The post simulation was did with the parasitic factors of the whole layout.The clock synthesizer based on the DLL can produce three output multiplication the reference clock frequency, using CMOS0.18um1P4M process, the supply voltage is1.8V, the overall layout area is about300X24um~2, duty ratio error less than2%, the clock jitter is less than12ps@800MHz, power consumption is about5mW.