Font Size: a A A

Research And Implementation Of Digital Intermediate Frequency Spread Spectrum Transceiver Using FPGA

Posted on:2009-07-18Degree:MasterType:Thesis
Country:ChinaCandidate:X Y WangFull Text:PDF
GTID:2178360242489391Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
At present, FPGA is one of the research hotspots in the hardware design field. It has been widely used in algorithm implementations and product prototype confirmation, because it not only has abundant logic elements, but also is highly integrated and can be configured flexibly according to different applications. With the substantial development of microelectronics technology in recent years, it is capable of realizing the more complex digital communication system. On the other hand, the spread-spectrum communication technology has been applied to military communication and civil communication extensively, it is the key technology of the 3rd Generation mobile communication standards and becomes the research and application focus in many countries. In future wireless communications, the spread-spectrum communication technology will play its advantages fully and it will be attracting more attention. This paper is mainly about design and implementation of digital intermediate frequency (IF) transceiver combined with the software defined radios (SDR) technology based on FPGA.This paper first introduced the overall architecture and parameters of digital intermediate frequency (IF) transceiver system, given the simple explanation of spread-spectrum code, QPSK modulation, scrambler circuit, descrambler circuit, differential encode and differential decode. And then, describe the details of hardware realization using FPGA and give the design parameters and simulation waveforms. Because the synchronous technology which holds the core status in entire communication system is the basis of the system normal operation, Therefore, we have made the detailed theoretical analysis to the carrier synchronization, the symbol synchronization and the spread-spectrum code synchronization's algorithm. At last, we proposed implementation schemes based on FPGA. We execute the system by coding in Verilog HDL and using IP Cores supplied by Altera Corporation on Quartus II 6.0 software platform.To different parts of the system, we do function simulations and post simulations with ModelsimSE simulation tool, analyze the simulation results with Debussy5.3 wave observation tool and compare the results with principles, thus improve and optimize the design. Finally, download the transmitter and receiver system to the FPGA development boards based on EP2C70F672C6 and EP2S180F1020C3 respectively. Observe the system's operation real-time with SignalTapII logic analyzer, analysis the key signal with oscilloscope and spectrum analyzer. And then obtain the hardware test results and draw a conclusion.
Keywords/Search Tags:FPGA, DSSS, Symbol synchronization, Carrier synchronization, Verilog HDL
PDF Full Text Request
Related items