Research And Implementation Of Digital Synchronization Technology In Broadband Demodulation System

Recently, spectrum resources become more and more strained with the development of the communications industry, thus the management and monitoring for radio signal has become particularly important. As the main equipment, the spectrum monitoring receiver is developing towards integration that combined high speed data transmission with fast modulation recognition and digital demodulation technology. At present, few companies such as Rohde, Schwarz and Agilent applied digital demodulation function in the spectrum monitoring receiver in the market, but the performance is not good for a long time demodulation and low efficiency monitoring. Therefore, there is an important significance to study the digital demodulation technology in spectrum monitoring equipment. And as a key technology of digital demodulation, the synchronous technology directly determines the demodulation performance.In this paper an IF digital demodulation synchronization system based on the phaselocked loop principle is designed and implemented. It analyzes the carrier Synchronization and symbol synchronization technology principle and conducted intensive studies for their implementation through literature researching. Focus on the defects of lager difference in steady state and a longtime synchronization establishment from the traditional synchronization system, this paper presents a new fast synchronization establishment solution by combining practical application platform. This solution is mainly composed of the carrier Synchronization, bit synchronization and PC controller. With the control function of PC controller for the bottom chip, it realized the calculation and modification of the relevant parameters from the synchronization system. So, FPGA can timely update the corresponding coefficients in synchronization loop to complete the process from coarse synchronization to fine synchronization. This solution not only could achieve the synchronization between large capture bandwidth and small difference steady, but also could handle the input signal element rate changing in real time. The results show that the synchronization establishment time in this solution is reduced by 5 to 10 times in the case of using the same hardware resources compared with the conventional synchronization system.In this paper, MATLAB simulation is used to verify the correctness of this solution in theory and FPGA development software and ModelSim analysis tool are used to verify its feasibility in practice. In addition, the actual test result on the hardware platform has achieved the expected goal. Therefore, the design of IF digital demodulation synchronization system in this paper has high engineering value.