Research And FPGA Implementation On Demodulator For DVB_S2 Digital Receiver

The technology of the satellite communication is developing rapidly in recent year.Due to the characteristics in the satellite communication of large distance and wide coverage,the application of the satellite communication technology has not only limited to traditional military field,but also the vast civilian areas.The use of the satellite communication in civilian areas has opened up a vibrant new markets.At the same time,the digital satellite broadcasting and TValong with the development of digital satellite communication technology get great progress.In order to apply to the demand of the market and the standard of the industry,the European telecommunications standards committee proposed DVB_S2 as the second generation satellite digital video broadcasting standard.The standard has range application,flexible configuration and system parameters and that has strong ability of error correction and large transmission capacity.As the technology of digital demodulation is one of the most key technologies of the whole DVB_S2 receiver,the study of DVB_S2 demodulator is also one of the hot spot research in recent years.This thesis takes the actual project tasks and technology development need,studying the following aspects for the design of DVB_S2 standard demodulator and implementation on FPGA.By the key technology research status analysis for carrier synchronization,frame synchronization and symbol synchronization,we compare the advantages and disadvantages of various options then eventually determine the coarse synchronization with pilot carrier,using the algorithm of M&M with fine L&R synchronization algorithm;For frame synchronization we use the method of difference related and pilot aided;We use Gardner algorithm for symbol synchronization.In FPGA implementation,because the M&M algorithm is similar to the algorithm structure of L&R,we analyze the realization process of the algorithm of M&M.To get the arctangent radian,we us CORDIC algorithm to achieve it.To implement DDS in NCO module,we use compressed ROM table method to realize the results then we compare it to the results of simulation in matlab.The realization of frame synchronization uses the state machine to control the whole operation process of the data,comparing the results of each module and the matlab simulation results.The implementation in symbol synchronization uses the pipeline to achieve logic operation.Finally we analyze the results of simulation in the DVB_S2 for QPSK modulation and the zero intermediate frequency signal demodulation.