Research And FPGA Implementation Of Synchronization Algorithms In Single-Carrier And Multi-Carrier Communication Systems

As an important part of the communication systems, synchronization technology, which is used to ensure the performance of communication systems, is always a hot research issue. Due to the power limitation, baseband signal processing under the conditions of low complexity is one of the difficulties in satellite communications. Single carrier modulation has the characteristics of low PAPR and low complexity, so satellite communication systems usually adopt the technology. Published since 2008, the second generation of terrestrial digital video broadcasting(DVB-T2) system using OFDM modulation technology has been widely known due to the advantages of high spectrum efficiency, flexible configuration parameters etc. This paper studies the synchronization technologies of both the SC-FDE system and the DVB-T2 system, especially the frame synchronization and sampling clock synchronization for the SC-FDE system and P1 symbol synchronization in the DVB-T2 system. The main contributions of this paper include:Firstly, for the single carrier satellite communication system, the main function of frame synchronization is to distinguish the "start" or "end" of the information frame and provide accurate starting position information for the receiver. The main role of sampling clock synchronization is to enable the receiver to sample signal in the best sampling time and guarantee the performance of the system. This paper studies the frame synchronization algorithm based on the PSC sequence and sampling clock synchronization algorithm based on the typical Gardner sampling clock synchronization algorithm. Based on high-order cumulants, this paper presents a synchronization lock detection algorithm for the sampling clock synchronization loop to generate a lock-indicated signal to control the subsequent modules. Compared with the existing synchronization locking detection algorithm, the main advantages of the new algorithm include:(1) the correct detection probability of the new algorithm can reach 100% when the SNR is higher than 3d B, which improves at least 1d B compared with the existing algorithms; when the SNR is less than 3d B, the correct detection probability of the new one remains above 65% at-5d B, and compared with the existing algorithms, the correct detection probability increases significantly;(2) since the high-order cumulants can eliminate the influence of noise, the decision can be determined by using a single threshold, which improves the practicability of the proposed algorithm, whereas a large number of simulations are required to determine the thresholds for other existing algorithms.Secondly, in the DVB-T2 system, as the header of T2 frame, the P1 symbol is used to detect the existence of T2 frame and realize the initial symbol synchronization. Study of P1 symbol synchronization has important significance for DVB-T2 system. The existing P1 symbol synchronization algorithms are investigated and compared thoroughly. For the SFN channel with poor characteristics, this paper proposes a new double-correlation-detection-based P1 symbol synchronization algorithm by using the special structure of the P1 symbol. Compared to the existing P1 symbol synchronization algorithms, the proposed algorithm can enhance the probability of detection at least about 1d B, and increases the P1 probability of decoding by at least 0.5d B under SFN channel. The new algorithm also has the similar complexity compared with that of the traditional double correlation detection algorithm. System level simulation verifies the reliability and feasibility of the new algorithm.Finally, the considered key modules, including the frame synchronization algorithm, sampling clock synchronization algorithm, and the P1 symbol synchronization and decoding algorithm, are implemented by using VHDL. Simulations and synthesis are performed by using the Modelsim software and the ISE software respectively. We complete the download test in the Xilinx ML605 development board. By comparing with the corresponding Matlab simulation results, the correctness of the implementation of the FPGA algorithm is verified.