Design Of SATA Host Controller Based On FPGA

SATA (Serial Advanced Technology Attachment) is a computer bus interface between host bus adapter and high-capacity storage device. Compared to Parallel ATA interface, SATA interface uses a pair of differential wires for data transmission and reception. In terms of speed, SATA 1.0 can achieve 150MB/s transfer speed, SATA 2.0 can achieve 300 MB/s transfer speed, the latest SATA 3.0 standard is to achieve 600MB/s transfer rate. In addition, SATA interface supports hot-swap, CRC on the data, command, and packet error checking. SATA is widely used at present, but there are rare independent research and development results in our country.The complete design of SATA Host Controller is given. On the hardware platform of FPGA, using Microblaze to process data command and interrupt command, PLB bus to transfer data, Block Ram as the storage medium, the data interaction is realized through SATA IP core. According to SATA protocol, the structure and modules at all levels are established. The modules such as Physical layer state machine, OOB control, Power reset, Link layer state machine, Cyclic Redundancy Check and Data scramble are designed and implemented. The data received from device after power up are collected to analyze the device status information.The controller is described by Verilog HDL language and functional simulation is implemented by ISE, using the logic analyzer Chipscope pro to debug. The codes are optimized to avoid competitive state and make the program more stable. At last, the controller is running correctly and consistent with the SATA protocol description by the plate test results.