| In the 21th century, the information system will come into our life, as the fomat of digital, plentiful, alternate, high-syncretized and multimedia . Without enough support of theory and technic , the image as the carrier of information should restrict the progress of society. ISP is the system of image processor, which is developed by Spreadtrum Inc. independently. It is used in several fields , such as digital camera and video phone etc. IEE shortened from Image Edge Ehancement is the important part in ISP system, which function is in processing effect of vision, denoising , compressing and decompressing. This module is connected with ARM by AHB in ISP system,and it is an accelerator .A part of work in the digital image processor can be dealed with afterwards , which is using universal computer system. The other should be dealed with in time . It is difficult to complete it only with an universal computer . So, it is necessary to design the ASIC (Application Specific Integrated Cricuit).As the increase of complexity of the chip, Verification will be the key step, and occupy 60%~80% percent time in develop of SOC (system on chip). To decrease the time of developing chip, it is necessary to adopt a new method of verification to increase the efficiency and coverage of verification.The ISP system is designed with the method of Top-Down, and IEE is a sub-module in it. To meet the aim of design, firstly analyzing the C-model supplied by soft part. Secondly, writing the design plan and describing the timing of interface. Finally, writing the RTL code using verilog.Furthermore, a new efficiency method of verification is used in this article to verify IEE completely. The method is to build a testbench based on VMM in which comparing the C-model with output of verilog. It is also need to prepare enough test cases to increase coverage and export the function and code coverage. According to the result of verification, IEE module can meet the require of design. |
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