SRAM Anti-radiation Hardening Design Under 65nm Bulk Silicon CMOS Technology

In our contemporary society,with the government's financial support and encouragement,the integrated circuit(IC)related industries are developing rapidly,and the functional size of the device is shrinking day by day,constantly breaking the limit to adapt to the transistor integration density on VLSI chips.Integrated circuits are widely used as the control center of electronic equipment,and the radiation environment faced by the aerospace,defense and military industries is more complex.This makes the research of anti-radiation reinforcement design imminent.Based on the 65nm CMOS process,this paper studies the memory cell reinforcement,analyzes the redundancy reinforcement technology,and proposes a New 14T SRAM(Read Write Separation 14T Static Random Access Memory,call RWS 14T SRAM)cell reinforcement structure based on the read-write separation technology.Then the basic performance and anti-radiation performance of the storage unit are simulated.The main contents are as follows:First,the working principle of the traditional 6T SRAM cell structure is briefly summarized.From the perspective of radiation resistance,especially the single event effect(Single Event Upset,referred to as SEU),the sensitive points of the memory cell are analyzed,and several methods to strengthen the SRAM cell are introduced.Secondly,in view of the advantages and disadvantages of the existing radiation-resistant SRAM cells,improvement methods are sought.The RWS 14T SRAM cell circuit with polarity reinforcement technology is proposed,and the reinforcement technology of redundant nodes is realized by adding transistors,so that the storage node does not change under the bombardment of high-energy particles.In the spectre software,the RWS 14T SRAM cell circuit read and write speed,cell stability and power consumption were tested and compared with the 6T cell,DICE cell and Quatro cell.Simulate high-energy particle bombardment,inject a corresponding current source at different nodes,analyze the anti-SEU ability of key nodes,and plan the layout of the memory cell.Finally,3D modeling is carried out to simulate the particle bombardment experiment.The experimental results show that under the 65nm process,when the voltage is 1.2V,the performance of the RWS 14T unit circuit and the 6T unit circuit are compared,the write speed is increased by about 5.1%,Read Static Noise Margin is increased by 20.7%,and the bit line write margin is improved That's 36.1%.At the same time,when the incident particle energy is 30Me V-cm~2/mg,when the key node is bombarded by high-energy particles at?=0~o,it is possible to keep the data stored in the memory cell from flipping.Moreover,the high-energy particles with different incident angles are bombarded at different key nodes,and the memory cell still has good anti-SEU ability,and they can be restored after LET=25MeV-cm~2/mg and the data is flipped.