ΣΔAD Converter's Improvement And Its Latter-stage Design

Sigma-Delta AD Converters, a series of oversampling Analog-to-Digital Converters with high resolution and low transition rate, are mainly applied in the field of audio and video signal processing. So far, ADS1271 with 24bit bandwidth introduced by TI has the highest bandwidth in industry. Generally, the analog part in a Sigma-Delta AD Converter modulator mainly decides design resolution and transition rate. While the transition rate, power dissipation and chip area of a digital decimation filter, which is the digital part, also has large influence on the performance of A/D or D/A Converters. One the other hand, decimation filters often have fixed orders, fixed coefficients and fixed output bit numbers, resulting in a specific decimation filter required by the resolution limitation of a given modulator.In order to solve problems mentioned above, this thesis introduces a decimation filter with flexible orders and output bit numbers, which is used in the Sigma-Delta AD Converters to realize the speech signal process in SOC. The research work is based on a taped-out Sigma-Delta modulator with 128 times oversampling rate, 3-order cascaded Switch-Capacitor structure and 14-bit resolution. In the design of the decimation filter, orders, coefficients and output bit numbers are all controlled by external signals. The filter can automatically select proper orders, coefficients and output bit numbers according to a given input signal with specific Signal to Noise Ratios (SNR). This character makes it possible that a flexible decimation filter can be considered as a standard unit in ASIC library to work together with different modulators and used in the test of a modulator with uncertain input resolution. The decimation filter is fit for 8~24 kHz input signals with SNR ranged from 62dB to 109dB. The design is implemented by 0.18μm 6-metal CMOS Technology, with chip area 1.48×1.48mm2. Besides, the design methods of multi-phase structure, Time Division Multiplexing (TDM) and reused module largely simplify circuit's structure and decrease chip's area.In order to test the chip performance and improve the design of modulator, the thesis also describes the testing scheme and analyzes the testing results: the chip's function is correct, but the output resolution is only about 6 bit, lower than the design goals; the direct reason for low performance is the influence of fabrication error on OTA's reference voltages and the mismatch of circuit parameters.Finally, the thesis proposes of several suggestions to improve the modulator design: reducing the power supply from DC 3.3V to DC 1.8V; using self-bias circuit to generate OTA's reference voltage values; improving the structure of 3-order modulator, adjusting circuit parameters and doing a system simulation of the new design. From the simulation result, it can be concluded that the output peak SNR is up to 108dB (equal to 18-bit effective output bit) in the ideal condition.