The Nios System Avalon From Peripherals (pwm) Design And Research

A Nios system is similar in traditional microcontroller or "computer on chip", because the Nios system contains peripherals device and memory. But the Nios system is different from other traditional microcontroller or "computer on chip" in many places.The Nios II processor is a configurable soft-core processor, as opposed to a fixed-microcontroller. In this context, "configurable" means that features can be added or removed on a system-by-system basis to meet performance or price goals. "Soft-core" means the CPU core is offered in "soft" design form (i.e., not fixed in silicon), and can be targeted to any Altera FPGA family. In other words, Altera does not sell "Nios II chips"; Altera sells blank FPGAs. It is the users that configure the Nios II processor and peripherals to meet their specifications, and then program the system into an Altera FPGA.Altera provides a set of peripherals commonly used in microcontrollers, such as timers, serial communication interfaces, general-purpose I/O, SDRAM controllers, and other memory interfaces. Designers can also create their own custom peripherals and integrate them into Nios II processor systems. For performance-critical systems that spend most CPU cycles executing a specific section of code, it is a common technique to create a custom peripheral that implements the same function in hardware. This approach offers a double performance benefit: the hardware implementation is faster than software; and the processor is free to perform other functions in parallel while the custom peripheral operates on data.This text describes the design flow to develop a custom SOPC Builder component (PWM) based Nios II IP core. Discussed some characteristic of Avalon bus and how to design slave Avalon Interface from hardware to software, at the some time we provided API to transfer by higher custom. Here the foundation is write the customer of high controls procedure. The total design is complete on the FPGA and gets the right result. This text has some guide meaning for embeded system develop and some design based IP core.