A Methodology Of IR-Drop Analysis For Full Custom IC Circuit Based On Pre-Layout

With the advance of semiconductor manufacturing, circuits with increasingly higher speed are being integrated at an increasingly higher density, which makes analysis and verification of power grid integrity more important. Power grid integrity includes four issues, namely, IR Drop analysis, ground bounce analysis, Ldi/dt from the pin inductance and EM analysis.This paper focuses on IR Drop analysis. Normally, we can't do IR Drop analysis before finishing layout design and DRC & LVS check. Parasitic resistor and capacitor are must for all these tools.This paper is focused on a methodology of IR Drop analysis for full custom IC circuit design based on PRE-LAYOUT. First we use Cadence schematic editor Composer as design platform, and then we get parasitic parameter by modeling resistor and capacitor on the schematic. Perl and Cadence Skill language are good coding languages to be used in this flow. By this methodology, we finished the power network IR Drop analysis, verification and optimization.