The Design And Realization Of Data Cache In 64 Bits CPU

Microprocessor is an indispensable device in information product. There are two types: generic and special application. And the design of microprocessor is very tough and chanllenge. This paper focus on the research and design of Cache in 64-bit high performance microprocessor, an National Science and Technology Ministry 863 project, using full customer design flow, which Take full use of EDA tools and improve the deficiency of customer design.At first, we analyse the importance of developing independence intelligence property core, IC design methods and full customer design flow. Then analyse cache in Multiprocessors, introduce the SMP and the methods to solve the Cache coherence; and introduce kinds of SCMP--POWER4-IBM, Hydra-Stanford, SMPDCA and compare them. Have ideas on four-core CPU cache.We detailed analyse the architecture and the theory of cache, detailed explain the full customer design of the Cache based on MIPS R4000 5-stage instruction architecture, include the circuit design, pre-layout simulation, layout design, layout verification, layout parameter extraction and post-layout simulation. There are two sections--datapath section and control unit. We put on the full-custom circuit and layout design in the data path section, and the synthesis method in the control unit. Realizing a havard structure, separate 4KB ICache and 4KB DCache, Direct map, virtually indexed and physical tagged, and LRU replacement strategy.