The Research On Power-Grid Fast Modeling And Hardware Acceleration For EDA Tools

With the IC technology level entering the very deep sub micron era, signal integrity problem is increasingly serious. The quality of the power grid design is one of the most important factors impacting the signal integrity. With the chip scale increasing, the number of nodes on power grid increases rapidly. This would be a high criterion to the requirement of the power grid simulation speed. In this dissertation, the simulation efficiency would be discussed from two viewpoints. One is to do research on the fast simulation model of power grid in traditional EDA tool environment. The other is to introduce hardware acceleration technique to EDA tool field and do research on its application in the power grid simulation.There are three physical effects on the power grid. Among them, IR-Drop effect and ground bounce effect impact the signal integrity while electro-migration impacts the reliability of VLSI design. The fast modeling methods of IR-Drop effect and ground bounce effect are discussed here. A kind of method has been introduced, which can estimate the ratio of power grid metal area to entire chip area quickly. In consideration of the IR-Drop effect in interconnect analysis of MEMS sensor measurement circuit, the mathematical model has been modified so that the measurement error of sensor is reduced.Simulation would consume seventy percent of the whole chip design cycle. Simulation speed is always the bottleneck in the chip design flow. Nowadays the simulation system pattern is still according to the general computer plus EDA tool. Here the software hardware acceleration is introduced to the simulation environment and the specific hardware simulation circuit is realized to execute tasks replacing EDA tool. This would improve the simulation speed greatly.First, the hardware implementation of basic matrix computation is presented. Then, the hardware implementation of a complex matrix computation--BSOR (Block Successive Over Relaxation) iterative method is discussed. Finally, multi-grid method is hardware implemented, which is the acceleration algorithm for power grid simulation. Because the power grid mathematical model is the huge matrix, the matrix partition approach is given here, which has the reference value to any other type of matrix computation based circuit simulation. Experimental results show that the hardware acceleration of EDA tool can improve the simulation speed by several orders of magnitude effectively. For example, the hardware acceleration implementation in this dissertation can improve three orders of magnitude. The hardware acceleration is a large field. Here it is introduced into EDA simulation field and a kind of hardware acceleration is implemented. Introduction of hardware acceleration in full-scale would be the EDA development trend.