Research And Implementation Of Key Techniques Of High Reliable Microprocessor Designs

In recent years, there has been a rapid increase' in the use of computer systems. Most applications require computer systems to work steadily and reliably. This trend has led to critical concerns with the validation of the reliability of the microprocessor, which is the heart of the computer system. Radiation and electromagnetic interference are two typical causes of microprocessor faults. The interference of Single Event Element (SEE) caused by radiation and electromagnetic interference is the focus of current high reliable microprocessor design techniques.Single Event Upset (SEU) phenomenon of SEE will not damage the circuit of the processor, but it can change the logic state of the circuit. As a result, the circuit will work incorrectly and failures will be brought in. SEU is a transient effect and occurs randomly, so it has become the main concern in SEE mitigation techniques of the high reliable microprocessor design.Special VLSI arts and crafts may be the most essential method to improve the reliability of the microprocessor. But the high cost makes it only fit for the military and aerospace applications. For those commercial reliable microprocessors, architecture level design techniques may be a better trade-off between cost, performance and reliability. Our work is significant both in theory and practicality.Traditional reliable microprocessor design techniques focus on improving the reliability of memories and sequential circuits. With the trends of reduced feature sizes, reduced supply and threshold voltages, SEU tolerance of combinational circuits is affected more than sequential circuits. It is expected to equal to the SEU rate of unprotected memory elements in future.Based on studying key techniques of the high reliable microprocessor design, this paper designed and implemented a prototype of high reliable microprocessors named HR8051. By testing and analyzing HR8051, this paper demonstrated the usefulness of our reliable microprocessor design techniques.First, this paper analyzes the impact of SEU, especially on the sequential circuit and the combinational circuit. Then, four key techniques of reliable microprocessor design are discussed.As traditional Triple Modular Redundancy (TMR) technique can only protect the sequential circuit, this paper adds time redundancy in to space redundancy. Two new redundancy techniques called Space-Time TMR (ST-TMR) and Enhanced ST-TMR (EST-TMR) with double edge triggered registers are presented in this paper, which improve fault tolerance of both the combinational circuit and the sequential circuit. ST-TMR is effective in protecting throughput logic circuit while EST-TMR is effective in protecting state-machine logic circuit. This paper also analyzes the principle and the character of Error Detecting and Correcting (EDAC) technique. According to the shortage of the Hamming code, this paper presented an advanced Hamming EDAC. This method decreased the incorrect detecting and correcting of traditional Hamming code.Based on the special architecture and function of ALU, this paper presents Berger code error detecting technique. The principle and character of the technique is analyzed and discussed.A new technique used to detect errors in the control flow by both software and hardware is presented in this paper, together with a field saving and recover strategy. Their algorithm and character is analyzed and discussed too.At last, based on the study of high reliable microprocessor design techniques, this paper implemented a prototype of high reliable microprocessors named HR8051. All the key techniques presented in this paper are implemented. By injecting faults and simulating, the result of the test show that HR8051 has higher reliability than the 8051 microcontroller which has not been hardened. As a result, the usefulness of all the techniques presented in this paper is proved...