Functional Verification Of A System On A Chip Based On The SPARCv8 Processor

As with fast-developing integrated circuit technology and design capabilities,chip design gets increasingly sophisticated with its scale expanding rapidly.Unfortunately,chip verification technology can not catch up in design and manufacturing development,and thus become the bottleneck of chip design process,hurting production efficiency.Faster and more functional verification technology uncovers design mistakes timely,which reduces development costs,shortens design periods,and maximizes potential profit.At the moment,main functional verification methods are simulation-based verification and formal verification.Simulation-based verification is extensible and can handle the large-scale design.Formal verification is perfect and accurate,but can only be applied to small-scale design or module-level verification.This thesis' s test object is design of a SoC(System on a Chip).This chip's processor is based on SPARC v8(Scalable Processor Architecture)instruction set architecture.Thanks to its high performance,low power consumption,and high reliability,this chip can meet requirements in a wide variety of space applications.It has been flowed successfully,and passed trial run and many times practical test.This chip has been launched to the space now.Recently,in order to meet market demand,designers of the SoC plan to carry out a large-scale promotion.Before that,this system needs to be verified more comprehensively.To verify this SoC in all aspects of functions,this thesis adopts simulation-based verification,which is the leading functional verification method in industry.The main work of this thesis are as follows:1.Present a targeted verification method,which adopts combination of directed and constraint-based random test cases,automatic results comparison,and functional coverage guidance.Technique of directed and constraint-based random test cases combination can generate stimulus for input.Platform of automatic results comparison can compare design results of operations and golden model of the correct expected output,which can help to rapidly locate design errors.The functional coverage is collected and evaluated to measure whether the design has been fully validated.2.Design and implement a verification platform with high degree of automation and scalability.To verify all aspects of a chip efficiently,usability and productivity of the verification platform are what matter most.This thesis designs a verification platform with high degree of automation and strong scalability,which can effectively shorten the verification time and guide follow-up projects.3.Set up a constraint-based random instruction generation platform.The platform can automatically and quickly generate a lot of legal instruction sequences in a short time,with strong flexibility of various parameters settings.At the same time,our platform provides verifiers with a configurable interface to generate new verification sequences more efficiently.