Design And Implementation Of SoC Functional Verification Automation System

Verification is probably the most difficult and important aspect of System-on-Chip (SoC) design. It is the only opportunity to find conceptual, functional, and implementation errors before the design is committed to silicon. For Chip design, verification must be an integral part of the design process from the start, along with synthesis, system software, bring up, and debug strategies. For many teams, verification takes 50%-80% of the overall design effort. In the electronic industry today, the combination of increasing complexity of todays ASIC and systems designs and relentless time-to-market (TTM) pressures has resulted in verification, especially functional verification, jumping to the top of the list of bottlenecks in the design and development of electronic products utilizing SoC.A transaction-based verification methodology (TBV) can be the most effective method to make functional verification. Based on the TBV methodology, a framework for functional verification automation solution is proposed in this dissertation. The main works are as follows:1. By studying the tools for function verification, a layered architecture is proposed in this dissertation. The layered architecture has a better reusability, and can be easily automated.2. The followed problems have been deeply researched: Integrate seamlessly with existing verification tools, design data abstraction, automated verification flow implement.3. Using Verilog and C language implement the layered architecture on UNIX operation system.4. A research is done for studying the reusable design principles of bus function model (BFM) and bus monitor for reusability.The functional verification framework is proposed in this dissertation can be apply in SoC system level, RTL level and gate level verification. We accumulated experiences to SoC functional verification.