Design Of High Speed Arithmetic Logical Unit In Digital Signal Processor

With the development of IC design and manufacture, and software design, Digital Signal Processor has been widely used in communications, multimedia, information appliances and other fields for its unique architecture and outstanding processing ability in calculating multimedia data. However the rapid growth of applications brings new challenges to DSP design. This paper searched some kinds of structure of present DSP processors, including the Single Instruction Multi Data (SIMD) structure.(1) After researching traditional ALU structure and all kinds of adders'internal structure, an ALU design method based on Truth Table. An optimized CSA carry chain, which fits for SIMD instructions, is researched. And this paper is dedicated to design a 32 bits fix point high performance DSP Core after researching some algorithms in sub-word parallelism ALU design.(2) After finishing ALU instruction set functional verification and carry out the optimization method and attempt to a ROM based design. This paper developed a way based on truth table to design circuit and an optimized carry chain based on CSA after analyzing character of this design. And then this paper tried to optimize the circuit by using CLA carry chain and analyzing the result. After that, this paper researched on structure and character of ROM circuit, according to the method to design ROM based logic, designed net list level ROM based CSA and optimized it, then this paper brought a method to justify ROM based design to traditional design.In the last chapter, this paper researched on the physical design flow of this circuit.