Design And Analysis Of A VLIW SMT Processor

DSP (Digital Signal Processor) is a kind of embedded processor for digital signal processing, which has powerful ability for numerical operation and is now widely used in fields of communication,military,control,electric equipment and so on. ILP(Instruction Level Parallelism) technology is a kind of method that can effectively enhance the performance of computer, as regards to high performance,low power and real time, most high performance DSPs take the VLIW(Very Long Instruction Word) structure. SMT(Simultaneous Multithreading) technology can translate TLP into ILP to exploit more parallelism. So it can further promote the performance of multi-issue processor to implement SMT on it.YHFT-D4 is a 32-bit fix-point DSP of high performance, which uses VLIW structure and can issue eight 32-bit instructions in parallel at the most. According to MOSI (Multi-Op Splitting Issue) micro-architechture presented by our research group, this dissertation designs a completely new dual-thread SMT processor YHFT-DSP/SMTOO by modifying YHFT-D4.The fetch unit of YHFT-D4 is modified to make the fetch bandwidth shared by two threads with different priority. The preferred thread of two threads always has the priority to fetch instructions, only when the preferred thread can't fetch instructions does the other thread uses the fetch bandwidth. A branch buffer is designed in the fetch unit to ensure that branch and the instructions in the branch delay slots can enter the pipeline correctly.Limited dynamical instruction scheduling, that is the execution packet splitting issue mechanism, is implemented by improving the issue unit of YHFT-D4.The splitting issue of execution packet makes the scheduling order of instructions different with the order in compile time, and it may lead to wrong execution result. So a write back buffer is designed to ensure the correct execution of programs, the execution results are first reordered by the buffer, then written back into registerfile.SMT can effectively improve the throughput and the usage of function unit, we evaluate the performance of YHFT-DSP/SMTOO with a group of benchmarks, it is shown that the IPC has an average gain of 24.65 %, and the usage of function unit has an average gain of 31.38 %.RTL level code is finished, and simulation verification is done on YHFT-DSP/SMTOO. DC is used to synthesize and optimize the design with Artisan's 0.18μm standard cells. It turns out that the critical timing path has increased by 1.2%, and the core area has increased by 30.32 %,chip area has increased by 8.86%.