Research On Test Compression For Digital IC

With chip designs advancing to VDSM (Very Deep Submicron) era, the design level of digital IC is becoming increasingly higher with shrinking feature sizes and more and larger density. To obtain high quality IC products, it is required to perform IC test for the products before manufacturing them, because it is one of the important ways to guarantee the quality of the finished product. While the ever-enhancing IC manufacturing abilities pose great challenges to IC test. While the current ATE fails the requirement because of its restricted storage, available pins and unbearable test application time. The previously proposed designs mostly require huge test data volume, forming a bottleneck that restricts high quality test. Test compression has been a heated research topic in recent years. Therefore it is significant for us to explore novel, effective test generation and test compression methods.This paper overviews the recent research work on delay testing, focusing fault set compaction and test data compression for scan designs, and approaches to delay testing are analyzed, pros and cons of each method is discussed. With the enhancement of IC manufacturing abilities, many new issues such as crosstalk, timing etc arise. Among them lots of novel test approaches to solve these problems require high test costs. Lately, various methods have been proposed to deal with the problems of ever-increasing test costs and test efficiency. The achieved good results prove the effectiveness of the previously presented algorithms; however they are mostly at the cost of extra hardware overhead. To alleviate the problems, we put forward a drastic test data scheme based on scan chain concealment and X-compact techniques for multiple scan designs. Adjustable width scan chain strategy is employed for test stimuli decompression, and test response takes the advantages of X-compact. A response shaper further minimizes the probability of fault masking. The enhanced broadcast-scan based mode for CUT (circuit under test) is able to deal with FFs (flip-fops) with the opposing values as well as the identical values. Two modes can handle the rest compact FF values after filling the unknown values: Under parallel mode, test vectors with the same corresponding bit values can be processed concurrently. And if there are such test vectors which have the corresponding opposite bit values as the existing test vectors, we also put them in parallel part. The second mode-serial mode deals with the rest compact test vectors. Due to the usage of inverter in parallel part, hardware overhead is decreased.The merits of proposed approach are as follows. Test storage requirement is reduced drastically, and test input/output pins, test channels coupled with test application time decrease, thus improving test compression ratio completely. The experimental results on benchmark circuits ISCAS'89 demonstrate the advantages mentioned above.SoC (System-on-Chip) has been one of the hot research topics with the rapid development of science and technology. As for IP core test compression, we also explored how to introduce the above mentioned method (drastic test compression) into this system harmoniously. And implementation of the idea is also given in this paper.