Simulation And FPGA Implementation Of Inner Coder/Decoder In DVB-T System

According to the transmission means used, digital televisions include terrestrial system, satellite system and cable system. Currently, as the globalized transmission standards, DVB-S and DVB-C have been adopted by most countries in the world. For the terrestrial digital video broadcasting standard, instead, International Telecommunications Union (ITU) recommends three standards involving European DVB-T(Digital Video Broadcasting - Terrestrial),American ATSC (Advanced Television System Committee) and Japanese ISDB-T (Terrestrial Integrated Services Digital Broadcasting). Compared with the other two terrestrial standards, DVB-T is proved to be more mature for both the technique utilized and the practical application.This thesis starts with a structure introduction of DVB-T system, providing the elaboration of all the modules involved in the transmitter side and the discussions on the implementation algorithms of the corresponding modules in the receiver side.Secondly, the general design flow for the baseband signal generation and reception simulation software platform implemented based on Microsoft Visual Studio 2005 is presented in the thesis, with the emphasis on the algorithm and implementation investigation of the inner coding/decoding and inner interleaving/deinterleaving modules of DVB-T system. In addition, on the basis of the implemented digital television simulation software with the changeable parameters, the thesis focuses on the analysis of the influence on the overall DVB-T system performance exerted by the hard decision and soft decisions utilized in the Viterbi decoding modules as well as different modulation schemes.Finally, the improvement in Viberbi decoding algorithm of inner decoding module is discussed in the thesis so as to make the Viterbi decoding is more feasible to be implemented on FPGA. Meanwhile, the logic design is optimized to save the hardware resource required. Focusing on the improvement in the algorithm of survival path information storage module, the thesis compares three different implementation schemes of the module from the viewpoint of hardware resource and throughout. Further, the traditional backtracking algorithm is improved in this thesis by writing and reading the survival path information in turn through 4 RAM. As a result, the windowing backtracking decoding output is achieved and the backtracking depth can be configured to satisfy the different system performance requirements.